View BL22P14_4739320.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

BL22P14 lcd type 8-bit otp mcu user m anu v 1 . 0 ( 2010-4-15) ? ? ? ? shanghai shanghai shanghai shanghai belling belling belling belling co., ltd. co., ltd. co., ltd. co., ltd.
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 1 of 33 lcd type 8-bit otp mcu BL22P14 1. general description BL22P14 is an 8-bit high performance single chip mi crocontroller. it provides two group configurable i/o ports, two timers and multiple lcd for household appliances. 2. features 8-bit cisc core compatible with motorola hc05 low power 1ua@5v in stop mode operating voltage: 2.5-5.5v(<=4mhz , 3.5-5.5v(<=8mhz) operating temperature: -40 ~85 4k*8bit rom 128byte ram lcd diver with 18*4, 19*3, 19*2 and 19*1 14 bidirectional i/o pa as keyboard interrupt source two external interrupt an 8-bit timer a 16-bit timer watch dog buzzer output lvd typical 3.3v lvr typical 3.0v 3 pin assignments
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 2 of 33
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 3 of 33 4. pin descriptions ssop48/lqfp48/sop28/sop24 pin name in/out share description pin description pa0 i/o bz0-buzzer output + pa1 i/o bz1-buzzer output - pa2 i/o pa3 i/o pfd output pa4 i/o pa5 i/o pa6 i/o pa7 i/o bit-programmable i/o port for schmitt trigger input or push-pull, each bit can be configured as a input with pull-high resistor or keyboard interrupt input pb0 i/o int0 pb1 i/o int1 pb2 i/o tmr0-timer0 input pb3 i/o tmr1-timer1 input pb4 i/o pb5 i/o bit-programmable i/o port for schmitt trigger input or push-pull, each bit can be configured as a input with pull-high resistor vss ground vlcd lcd voltage supply v1 v2 lcd filter capacitor com0 o com1 o com2 o com output of lcd com3/seg18 o com or seg of lcd seg17~seg0 o seg output of lcd osc4 o osc3 i 32768hz crystal oscillator
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 4 of 33 vdd power supply osc2 o osc1 i crystal oscillator or rc clock rstb i vpp system reset input 5. function descriptions 5.1 block diagram 5.2 address spaces $0000-$006f: control registers $0070-$007f: lcd data $0080-$00ff: ram $0100-$0fff: reserved $1000-$1fff: otp rom 5.3 control registers register name address r/w reset value pa $00 r/w 0000 0000
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 5 of 33 ddra $01 r/w 0000 0000 pb $02 r/w --00 0000 ddrb $03 r/w --00 0000 kbim $04 r/w 0000 1000 pbpr $05 r/w --00 0000 t0d $06 r/w 0000 0000 t0c $07 r/w 00-0 0000 t1dh $08 r/w 0000 0000 t1dl $09 r/w 0000 0000 t1c $0a r/w 0000 0000 intc0 $0b r/w --00 0000 intc1 $0c r/w 0000 0000 bzcr $0d r/w 0000 --00 mcr1 $0e r/w 00u- --00 mcr2 $0f r/w 0000 0000 rstfr $10 r/w ---- rrrr lcdd[9:0] $79-$70 w xxxx xxxx lcdcon $7a r/w 0000 0000 note: ? ?? ? - : not used; x: undefined; u: determined by opbit[4]; r: determined by reset type 5.4 clock device supplies four clock sources: crystal oscilla tor, external rc, rtc and wdt. first three clock sources can be as system clock fsys and all can be as internal clock fs. 5.4.1 system clock: fsys system clock is main operate clock for device. it i s configured by otp option bit fsys1, fsys0 to select a clock source. fsys1 fsys0 00 / 11 fsys=fosc/2 01 fsys=frc/2 10 fsys=frtc/2 5.4.2 internal clock: fs fs is the clock of buzzer, rtc interrupt, time base interrupt, lcd and watchdog. it is configured by otp option bit fs1, fs0 to select a clock source. if rtc or wdt is selected, device will still operate in stop mode. fs1 fs0 00 / 11 fs=fsys
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 6 of 33 01 fs=frtc 10 fs=fwdt 5.4.3 crystal oscillator crystal oscillator provides the clock of 455khz-8mh z. a crystal should be connected between the pin of osc1 and osc2. 5.4.4 external rc oscillator using external rc oscillator, a resistor between os c1 and vss is required. the value of resistor 800k ~40k , the frequency of clock will be 400khz~8mhz. osc2 can output clock of fsys if connecting a resistor from osc2 to vdd. however, the frequency of oscillator may vary with vdd, temperature and chip itself due to process variations. it is therefore, not suitable for timing sensitive operat ions where accurate frequency is desired. 5.4.5 rtc oscillator rtc oscillator provides the clock of 32768hz. a cry stal should be connected between the pin of osc3 and osc4. if it is the clock source of fs, rtc oscillator will still work in stop mode. the rtc oscillator circuit can be controlled to osc illate quickly by setting the qosc bit (bit 3 of register of mcr2). it is recommend to tur n on the quick oscillating function upon power on and then turn it off after 2 seconds. frequency of crystal value of c1/c2 8mhz 0/10p 4mhz 0/10p/20p 455khz 100p/200p
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 7 of 33 5.4.6 wdt oscillator wdt is a dedicated rc oscillator and output clock o f t=65us@5v. if it is the source of fs, rtc oscillator will still work in stop mode. the po wer is only 3ua@5v. 5.5 low power mode there are two low power modes: stop and wait. in stop mode, fsys is turn off and can be waked up by : keyboard interrupt. external interrupt. interrupt from module whose clock source is from r tc oscillator or wdt. in wait mode, only turn off clock of cpu and all in terrupt can wake it up. 5.6 reset BL22P14 can be reset in four ways: 1) by external power-on-reset 2) by the external reset input pin(p12) pulled low 3) by the digital watchdog peripheral timing out 4) by low voltage reset (lvr) there is a dedicated register to write reset type. rstfr ($10): reset flag register .7-.4 not used .3 rstf3 0: no wdt reset 1: wdt reset write 0 to clear the bit, write 1 is null. .2 rstf2 0: no lvr reset 1: lvr reset write 0 to clear the bit, write 1 is null. .1 rstf1 0: no res reset 1: res reset
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 8 of 33 write 0 to clear the bit, write 1 is null. .0 rstf0 0: no power on reset 1: power on reset write 0 to clear the bit, write 1 is null. 5.7 i/o ports there are two group i/o ports: pa and pb. pa has 8 i/o ports and pb has 6 i/o ports. all ports have pull up resistors. pa has the function o f keyboard interrupt. the control registers are pa, pb, ddra, ddrb, kbim and pbpr. pa ($00): data register of port a .7-.0 pa[7:0] pa is the data register for port a. ddra($01): data direction register of port a .7-.0 ddra[7:0] 00000000 ddra is used to select data direction of pa. when ddrai is 0, pai is input; when ddrai is 1, pai is output. pb ($02): data register of port b .5-.0 pb[5:0] pb is the data register for port b. ddrb($03): data direction register of port b .5-.0 ddrb[5:0] ddrb is used to select data direction of pb. when ddrbi is 0, pbi is input; when ddrbi is 1, pbi is output. kbim($04): keyboard interrupt mask register .7-.0 kbe[7:0] kbim is configured to enable keyboard interrupt. wh en kbei is 1, keyboard interrupt of pai is turn on, pai keeps input and it s pull up resistor is effective. besides, if needing keyboard interrupt active, kbie (bit 3 of register of intc0) should be 1. when kbei is 0, keyboard interrupt of pai is turn off. pbpr($05): portb pull-up register .5-.0 pbp[5:0] pbpr is configured to enable pull up resistors of p b. when pbpi is 0, resistor of pbi is ineffective. when pbpi is 1, resistor o f pbi is effective. when pb is output, pbpr is no effect. 5.8 lcd lcd drives 4*18 at most. when the clock of lcd come s from rtc oscillator or wdt oscillator, lcd will still operate in stop mode. lcd memory the memory of lcd is located at 70h-79h. any data w ritten into 70h-79h will affect lcd
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 9 of 33 display. when written 1, the corresponding bit is turn display on; when written 0, the corresponding bit is turn display off. before writi ng data to memory, the memory is inconstant. lcd register- lcdcon lcdcon($7a): lcd control register .7-.4 ps[3:0] 0000 dividing frequency of clock source 0000 1/2 5 0001 1/2 6 0010 1/2 7 0011 1/2 8 0100 1/2 9 0101 1/2 10 0110 1/2 11 0111 1/2 12 1000 1/2 13 1001 1/2 14 1010 1/2 15 .3-.1 dbs [2:0] 000 duty/bias select 000: 1/4 duty 1/3 bias(com0-com3 seg0-seg17) 001: 1/3 duty 1/3 bias(com0-com2 seg0-seg18) 010: 1/2 duty 1/2bias(com0-com1 seg0-seg18) 011: 1/3 duty 1/2bias(com0-com2 seg0-seg18) others: static(com0-com2 seg0-seg18) .1 not used .0 lcdon 0 0: all com/seg output high 1: lcd can display clock of lcd the clock source of lcd is fs, and dividing frequen cy is set by bit 4-7 of lcdcon. usually, the frame frequency is set at 25hz to 250h z. if wdt is the clock source, dividing frequency shou ld be1/2 5 ~ 1/2 8 . the frame frequency when wdt is clcok source (hz)
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 10 of 33 lcd frequency static 1/2duty 1/3duty 1/4duty fs/2 5 =512 hz 512 256 171 128 fs/2 6 =256 hz 256 128 85 64 fs/2 7 =128 hz 128 64 43 32 fs/2 8 =64 hz 64 32 21 16 if rtc oscillator is the clock source, dividing fre quency should be1/2 6 ~ 1/2 9 . the frame frequency when rtc is clcok source(hz) lcd frequency static 1/2duty 1/3duty 1/4duty fs/2 6 =512 hz 512 256 171 128 fs/2 7 =256 hz 256 128 85 64 fs/2 8 =128 hz 128 64 43 32 fs/2 9 =64 hz 64 32 21 16 other dividing frequency (1/2 10 ~1/2 15 ) is used when osc or rc is clock source. lcd drive voltage vlcd is the voltage source of lcd and divided to fo ur voltage level by internal resistors. vlcd may connect to vdd or other voltage. two capac itors connecting to v1 and v2 will improve stability for display. com/seg output the output number can be 4 com and 18 seg (48pin), 4 com and 8 seg (28pin and 24pin).com3 and seg18 are at common pin. com3 is ef fective only at 1/4duty mode and other mode is seg18. pin duty drive number bias
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 11 of 33 1 static 191 1/3 1/2 192 1/2 1/3 193 1/3 48 1/4 184 1/3 1 static 91 1/3 1/2 92 1/2 1/3 93 1/3 24 or 28 1/4 84 1/3 com and seg output wave static 1/2 duty 1/2bias
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 12 of 33 1/3 duty 1/3bias 5.9 timer - timer0 timer0 is an 8bit count-up counter. the counter clo ck source may come from fsys or rtc time-out signal or external source. using exter nal clock input from tmr0 (pb2) allows the user to count external events, measure t ime internals or pulse widths or generate an accurate time base. while using the int ernal clock allows the user to generate an accurate time base. there is a data register - t0d. before use, a data must be written to t0d. timer0 will count from $00 to this data and generate an interru pt. then counter restart from $00. timer0 has three operate mode: timer mode the timer clock comes from internal selected clock source. event mode to count external signal from tmr0, may count up w hen the signal is from low to high or high to low. pulse width measure mode to measure pulse width from tmr0. when te is 1, timer0 will start counting after tmr0 receives a transient from low to high(from high to low when te is 0) until tmr0 re turns to the original level and resets the ton. (note: ton is the enable of timer0, and only automa tic reset at pulse width measure mode. if other two modes, re setting ton must be finished by program.) in other words, only one cycl e measurement can be made until ton is set. then data reading from t0d is the value of pulse width. in the case of counter overflows, the counter is reload fr om the counter preload register and issues an interrupt request as other two modes. and the value of pulse width
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 13 of 33 must add the time of generating the interrupt. it has two registers: t0d t0c t0d ($06): timer0 data register .7-.0 t0d[7:0] 00000000 the data register of timer0 is writable and readabl e. when writing it, this data is the overflow data and timer0 will count from $00 to this data driven by internal or external signal. when reading, it is the real-ti me counting data. if writing to t0d, new overflow data will be effective in next co unting cycle. when ton is 0, writing to t0d will clear the coun ting data, and count from $00 after ton is set. but if do not writing to t0d when ton is 0, it will count from previous data which timer0 stop at. t0c ($07): timer 0 control register .7-.6 tm[1:0] 00 mode select 00: timer0 not work 01: event mode, and setting pb2 input 10: timer mode 11: pulse wide mode, and setting pb2 input .5 not used .4 ts 0 internal clock source select, ineffective in event mode. 0: fsys as clock source 1: rtc time-out signal as clock source .3 ton 0 counting enable bit 0: timer0 disable 1: timer0 enable .2 te 0 defining active edge of counting, ineffective in ti mer mode. 0: active on low to high 1: active on high to low .1-.0 ps[1:0] 00 dividing frequency select, ineffective in event mod e. the clock source is select by ts. 00: 1 01: 1/4 10: 1/16 11: 1/64 the overflow of timer0 can be applied to a pfd outp ut (programmable frequency divider)
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 14 of 33 at pa3 by option. 5.10 timer C timer1 timer1 is a 16bit count-up counter. the counter clo ck source may come from fsys or rtc time-out signal or external source or overflow from timer0. using external clock input from tmr1 (pb3) allows the user to count exte rnal events, measure time internals or pulse widths or generate an accurate time base. there are two data register- t1dh and t1dl. before use, data must be written to t1dh and t1dl. timer1 will count from $0000 to this data and generate an interrupt. then counter restart from $0000. timer1 has three operate mode: timer mode the timer clock comes from internal selected clock source. event mode to count external signal from tmr1, may count up w hen the signal is from low to high or high to low. pulse width measure mode to measure pulse width from tmr1. when te is 1, timer0 will start counting after tmr1 receives a transient from low to high(from high to low when te is 0) until tmr1 re turns to the original level and resets the ton. (note: ton is the enable of timer1, and only automa tic reset at pulse width measure mode. if other two modes, re setting ton must be finished by program.) in other words, only one cycl e measurement can be made until ton is set. then data reading from t1dh and t 1dl is the value of pulse width. in the case of counter overflows, the counte r is reload from the counter preload register and issues an interrupt request as other two modes. and the value of pulse width must add the time of generatin g the interrupt. it has three registers: t1dh t1dl t1c t1dh ($08): timer 1 data register (high byte) .7-.0 t1dh[7:0] t1dl ($09): timer 1 data register (low byte) .7-.0 t1dl[7:0] the data registers of timer1 are writable and reada ble. when writing it, this data is the overflow data and timer1 will count from $00 00 to this data driven by internal or external signal. when reading, it is th e real-time counting data. if writing to the data registers, new overflow data wi ll be effective in next counting cycle. when ton is 0, writing to the data registers will clear the counting data, and count from $00 after ton is set. but if do not writ ing to the data registers when ton is 0, it will count from previous data which timer1 stop at. one point must be note: there are two data register s, so it can not read or write
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 15 of 33 data synchronously. when writing, it must write t1d l at first and then t1dh. when reading, it must read t1dh at first and then t 1dl. t1c ($0a): timer 1 control register .7-.6 tm[1:0] 00 mode select 00: timer0 not work 01: event mode, and setting pb3 input 10: timer mode 11: pulse wide mode, and setting pb3 input .5-.4 ts[1:0] 00 internal clock source select, ineffective in event mode. 00: fsys as clock source 01: rtc time-out signal as clock source 10: ftbi time base interrupt as clock source 11: ftmr0 overflow from timer0 as clock source .3 ton 0 counting enable bit 0: timer1 disable 1: timer1 enable .2 te 0 defining active edge of counting, ineffective in ti mer mode. 0: active on low to high 1: active on high to low .1-.0 ps[1:0] 00 dividing frequency select, ineffective in event mod e. the clock source is select by ts. 00: 1 01: 1/4 10: 1/16 11: 1/64 the overflow of timer0 can be applied to a pfd outp ut (programmable frequency divider) at pa3 by option. 5.11 interrupt the device provides two external interrupts, two in ternal timer interrupts, an internal time base interrupt, an internal real time clock interru pt, eight keyboard interrupts, a software interrupt and an external reset. interrupts pc addr ess and priority are in the following table (priority is from low to high). address interrupt 1fe0:1fe1 reserved 1fe2:1fe3 reserved
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 16 of 33 1fe4:1fe5 reserved 1fe6:1fe7 reserved 1fe8:1fe9 reserved 1fea:1feb reserved 1fec:1fed reserved 1fee:1fef tbi 1ff0:1ff1 rtci 1ff2:1ff3 t1i 1ff4:1ff5 t0i 1ff6:1ff7 kbi 1ff8:1ff9 int1 1ffa:1ffb int0 1ffc:1ffd swi 1ffe:1fff reset the interrupt control registers intc0 and intc1 are used to set enable/disable status and interrupt request flags. once an interrupt subrouti ne is serviced, other interrupts are all blocked. this scheme may prevent any further interr upt nesting. all these interrupts except software interrupt supp ort a wake-up function. the request flags of kbi, int0 and int1 are 0 if relevant interrupt is turn off. but the request flags of t0i, t1i, rtci and tbi are not aff ected by enable bit. intc0 ($0b): interrupt control register 0 .7-.6 not used .5 kbie 0 keyboard interrupt enable/disable 0: kbi disable 1: kbi enable .4 kbif 0 keyboard interrupt flag 0: kbi has not interrupt request 1: kbi has interrupt request .3 int1e 0 external interrupt 1 enable/disable 0: int1 disable 1: int1 enable and setting pb1 input with pull-up resistor .2 int1f 0 external interrupt 1 flag 0: int1 has not interrupt request 1: int1 has interrupt request .1 int0e 0 external interrupt 0 enable/disable 0: int0 disable 1: int0 enable and setting pb0 input with pull-up resistor
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 17 of 33 .0 int0f 0 external interrupt 0 flag 0: int0 has not interrupt request 1: int0 has interrupt request intc1 ($0c): interrupt control register 1 .7 tbie 0 time base interrupt enable/disable 0: tbi disable 1: tbi enable .6 tbif 0 time base interrupt flag 0: tbi has not interrupt request 1: tbi has interrupt request .5 rtcie 0 real time clock (rtc) interrupt enable/disable 0: rtci disable 1: rtci enable .4 rtcif 0 rtc interrupt flag 0: rtci has not interrupt request 1: rtci has interrupt request .3 t1ie 0 timer1 interrupt enable/disable 0: t1i disable 1: t1i enable .2 t1if 0 timer1 interrupt flag 0: t1i has not interrupt request 1: t1i has interrupt request .1 t0ie 0 timer0 interrupt enable/disable 0: t0i disable 1: t0i enable .0 t0if 0 timer0 interrupt flag 0: t0i has not interrupt request 1: t0i has interrupt request 5.12 low voltage detect - lvd lvd provides the function to monitor voltage supply of chip. the typical lvd voltage is 3.3v. lvde (bit 7 of mcr1) is enable bit and makes lvd active if it is set. lvdf (bit 5 of mcr1) is flag of lvd and is 1 when vdd is lower t han 3.3v.
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 18 of 33 5.13 watch dog timer - wdt the wdt clock source is implemented by fs. the time r is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. wdt can be disabled by clearing wdte (bit 7 of mcr2 ) and be cleared by wdtc (bit 5 of mcr2). wdt is a 16bit timer and will make the device reset when counting to 2 16 . overflow time is: 65536*65us=4.2s (fs=fwdt) 65536*30.5us=2s (fs=frtc) 65536*0.5us=32.7ms 4mhz crystal, fs=fosc/2 5.14 buzzer bz0 and bz1 are buzzer driving output pair. if will ing to use the function, the related pa port should be set as an output. the clock source i s from fs. the buzzer is controlled by register bzcr. bzcr ($0d): buzzer control register .7-.5 ps[3:0] 0000 dividing frequency of fs 0000: fs/2 12 0001: fs/2 11 0010: fs/2 10 0011: fs/2 9 0100: fs/2 8 0101: fs/2 7 0110: fs/2 6 0111: fs/2 5 1000: fs/2 4 1001: fs/2 3 1010: fs/2 2 others: fs/2 .3-.2 not used .1 bz1e 0 0: bz1 disable 1: bz1 enable .0 bz0e 0 0: bz0 disable 1: bz0 enable 5.15 timer base timer base offers a periodic time out period to gen erate a regular internal interrupt. its time out period ranges from fs/2 12 to fs/2 15 selected by bit 5 and bit 4 of mcr2. if time
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 19 of 33 base time out occurs, the related interrupt request flag is set. 5.16 real time clock - rtc rtc is operated in the same manner as time base tha t is used to supply a regular internal interrupt. its time out period ranges from fs/2 8 to fs/2 15 selected by bit 2 and bit 0 of mcr2. if rtc time out occurs, the related interrupt request flag is set. rtc time out signal also can be applied to be a clock source of timer f or getting a longer time out period. rtc and time base use the same 15bit counter which is cleared only by system reset. so the first time out period of rtc or time base is un certain. 5.17 miscellaneous control register there are two miscellaneous control registers to co ntrol some functions. mcr1 ($0e): miscellaneous control register 1 .7 lvde 0 0: lvd disable 1: lvd enable .6 lvdf 0 0: vdd is higher than v lvd 1: vdd is lower than v lvd .5 lvre 0: lvr disable 1: lvr enable .4-.2 not used .1 pfde 0 0: pfd disable 1: pfd enable .0 pfdc 0 0: pfd clock is from time out of timer0 1: pfd clock is from time out of timer1 note: pfd is share with pa3. if outputting pfd, pa3 shou ld be output and data register of pa3 must be written 0. mcr2 ($0f): miscellaneous control register 2 .7 wdte 0 0: wdt disable 1: wdt enable .6 wdtc 0 0: useless 1: clear wdt note: when read this bit, it is always 0 . .5-.4 tbps[1:0] 00 time base interrupt period select 00: 2 15 *fs 01: 2 14 *fs
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 20 of 33 10: 2 13 *fs 11: 2 12 *fs .3 qosc 0 quickly oscillating select 0: quickly oscillating enable 1: quickly oscillating disable .2-.0 rt[2:0] 000 rtc interrupt period select 000: 2 15 *fs 001: 2 14 *fs 010: 2 13 *fs 011: 2 12 *fs 100: 2 11 *fs 101: 2 10 *fs 110: 2 9 *fs 111: 2 8 *fs 5.18 opbit opbit is a special byte in otp rom and used to conf igure some initial functions for the device. opbit is set when otp written. .7 encr 0: otp read protection 1: otp can be read .6 not used .5 lcd control in stop mode 0 lcd on in stop mode 1 lcd off in stop mode .4 lvreo 0: lvr off 1: lvr on .3-.2 fs[1:0] 00 11 fs=fsys 01 fs=frtc 10 fs=fwdt .1-.0 fsys[1:0] 00 11 fsys=fosc/2 01 fsys=frc/2 10 fsys=frtc/2 6. electrical data 6.1 absolute maximum ratings (t a =25 )
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 21 of 33 parameter symbol condition rating unit supply voltage v dd - v ss -0.3 to v ss +6.5 v input voltage v i all ports v ss -0.3 to v dd +0.3 v operating temperature t a - -40 to +85 storage temperature t s - -65 to +150 6.2 dc electrical characteristics (t a =25 vdd=2.7-5.5v) parameter sym. condition min typ max unit oscillator frequency <=4mhz 2.5 - 5.5 v operate voltage v dd oscillator frequency <=8mhz 3.5 5.5 v lcd operate voltage v lcd - 2.5 - 5.5 v input high voltage v ih1 all ports 0.7v dd - v dd v input low voltage v il1 all ports 0 - 0.3v dd v i/o ports source current i oh v oh =0.9v dd 5 12 - ma i/o ports sink current i ol v ol =0.1v dd 10 20 - ma pull-up resistors r ph pa, pb 10 25 40 k lvr v lvr - 2.7 3.0 3.3 v lvd v lvd - 3.0 3.3 3.6 v dynamic working current i dd 4mhz clock - 3 5 ma stop mode, lvr off, lcd off - - 1 ua stop mode, lvr on, lcd off - 10 15 ua standby working current i stb stop mode, lvr off, lcd on - 20 30 ua 7. instruction set 7.1 addressing modes the addressing modes define the manner in which an instruction is to obtain the data
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 22 of 33 required for its execution. there are 8 modes: 1) inherent 2) immediate 3) direct 4) extended 5) indexed, no offset 6) indexed, 8-bit offset 7) indexed, 16-bit offset 8) relative 7.1.1 inherent addressing mode in inherent addressing mode, all information requir ed for the operation is already inherently known to the cpu, and no external operan d from memory or from the program is needed. the operands, if any, are only the index register and accumulator, and are always 1-byte instructions. 7.1.2 immediate addressing mode in the immediate addressing mode, the operand is co ntained in the byte immediately following the opcode. this mode is used to hold a v alue or constant which is known at the time the program is written and which is not change d during program execution. these are 2-byte instructions, one for the opcode and one for the immediate data byte. 7.1.3 direct addressing mode the direct addressing mode is similar to the extend ed addressing mode except the upper byte of the operand address is assumed to be $00. t hus, only the lower byte of the operand address needs to be included in the instruc tion. direct addressing allows you to efficiently address the lowest 256 bytes in memory. this area of memory is called the direct page and includes on-chip ram and i/o regist ers. direct addressing is efficient in both memory and time. direct addressing mode instru ctions are usually two bytes, one for the opcode and one for the low-order byte of the op erand address. 7.1.4 extended addressing mode in the extended addressing mode, the address of the operand is contained in the two bytes following the opcode. extended addressing ref erences any location in the mcu memory space including i/o, ram, rom and eprom. ext ended addressing mode instructions are three bytes, one for the opcode an d two for the address of the operand. 7.1.5 indexed, no offset addressing mode in the indexed, no-offset addressing mode, the effe ctive address of the instruction is contained in the 8-bit index register. thus, this a ddressing mode can access the first 256 memory locations. these instructions are only one b yte. 7.1.6 indexed, 8-bit offset addressing mode in the indexed, 8-bit offset addressing mode, the e ffective address is obtained by adding
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 23 of 33 the contents of the byte following the opcode to th e contents of the index register. this mode of addressing is useful for selecting the kth element in an n element table. to use this mode, the table must begin in the lowest 256 m emory locations and may extend through the first 511 memory locations (ife is the last location which the instruction may access). indexed 8-bit offset addressing can be use d for rom, ram, or i/o. this is a 2-byte instruction with the offset contained in the byte following the opcode. the content of the index register (x) is not changed. the offset b yte supplied in the instruction is an unsigned 8-bit integer. 7.1.7 indexed, 16-bit offset addressing mode in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the 8-bit index register and the two by tes following the opcode. the content of the index register is not changed. these instructio ns are three bytes, one for the opcode and two for a 16-bit offset. 7.1.8 relative addressing mode the relative addressing mode is used only for branc h instructions. branch instructions, other than the branching versions of bit-manipulati on instructions, generate two machine-code bytes: one for the opcode and one for the relative offset. because it is desirable to branch in either direction, the offset byte is a signed twos-complement offset with a range of C127 to +128 bytes (with respect to the address of the instruction immediately following the branch instruction). if t he branch condition is true, the contents of the 8-bit signed byte following the opcode (offs et) are added to the contents of the program counter to form the effective branch addres s; otherwise, control proceeds to the instruction immediately following the branch instru ction. 7.2 instruction type there are 65 instructions in cpu, and can be divide d into 5 types. 1) register/memory instructions 2) read/modify-write instructions 3) branch instructions 4) control instructions 5) bit manipulate instructions 7.3 instruction set status instruction operation function h i n z c address ing mode opcode opdata #cycle adc #opr adc opr adc opr adc opr,x add with carry a (a)+(m)+(c) * - * * * imm dir ext ix2 a9 b9 c9 d9 ii dd hh ll 2 3 4 5
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 24 of 33 adc opr,x adc ,x ix1 ix e9 f9 ee ff ff 4 3 add #opr add opr add opr add opr,x add opr,x add ,x add without carry a (a)+(m) * - * * * imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and #opr and opr and opr and opr,x and opr,x and ,x logical and a (a) (m) - - * * - imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr,x asl ,x arithmetic shift left (same as lsl) c 0 b7 b0 - - * * * dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr,x asr ,x arithmetic shift right c b7 b0 - - * * * dir 1.1.1.1.1 inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc)+2+rel ? c=0 - - - - - rel 24 rr 3 bclr n opr clear bit n mn 0 - - - - - dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) 11 13 15 17 19 1b dd dd dd dd dd dd 5 5 5 5 5 5
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 25 of 33 dir(b6) dir(b7) 1d 1f dd dd 5 5 bcs rel branch if carry bit set (same as blo) pc (pc)+2+rel ? c=1 blo ? - - - - - rel 25 rr 3 beq rel branch if equal pc (pc)+2+rel ? z=1 - - - - - rel 27 rr 3 bhcc rel branch if half carry bit clear pc (pc)+2+rel ? h=0 - - - - - rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc)+2+rel ? h=1 - - - - - rel 29 rr 3 bhi rel branch if higher pc (pc)+2+rel ? (c z )=0 - - - - - rel 22 rr 3 bhs rel branch if higher or same pc (pc)+2+rel ? c=0 - - - - - rel 24 rr 3 bit #opr bit opr bit opr bit opr,x bit opr,x bit ,x bit test accumulator with memory byte (a) (m) - - * * - imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc)+2+rel ? c=1 - - - - - rel 25 rr 3 bls rel branch if lower or same pc (pc)+2+rel ? (c z )=1 - - - - - rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc)+2+rel ? i=0 - - - - - rel 2c rr 3 bmi rel branch if minus pc (pc)+2+rel ? n=1 - - - - - rel 2b rr 3 bms rel branch if interrupt mask set pc (pc)+2+rel ? i=1 - - - - - rel 2d rr 3 bne rel branch if not equal pc (pc)+2+rel ? z=0 - - - - - rel 26 rr 3 bpl rel branch if plus pc (pc)+2+rel ? n=0 - - - - - rel 2a rr 3
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 26 of 33 bra rel branch always pc (pc)+2+rel - - - - - rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc)+2+rel ? mn=0 - - - - * dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc)+2 - - - - - rel 21 rr 3 brset n opr rel branch if bit n set pc (pc)+2+rel ? mn=1 - - - - * dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 dir(bo) 10 dd 5
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 27 of 33 bset n opr set bit n mn 1 - - - - - dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc)+2 push(pcl);sp (sp)- 1 push(pch);sp (sp)- 1 pc (pc)+rel - - - - - rel ad rr 6 clc clear carry bit c 0 - - - - 0 inh 98 2 cli clear interrupt mask i 0 - 0 - - - inh 9a 2 clr opr clra clrx clr opr,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 - - 0 1 - dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp #opr cmp opr cmp opr cmp opr,x cmp opr,x cmp ,x compare accumulator with memory byte (a) -(m) - - * * * imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr,x com ,x complement byte (ones complement) m $ff-(m) a $ff-(a) x $ff-(x) m $ff-(m) m $ff-(m) - - * * 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx #opr cpx opr cpx opr cpx opr,x compare index register with memory byte (x) -(m) - - * * * imm dir ext ix2 a3 b3 c3 d3 ii dd hh ll 2 3 4 5
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 28 of 33 cpx opr,x cpx ,x ix1 ix e3 f3 ee ff ff 4 3 dec opr deca decx dec opr,x dec ,x decrement byte m (m)-1 a (a)-1 x (x)-1 m (m)-1 m (m)-1 - - * * - dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor #opr eor opr eor opr eor opr,x eor opr,x eor ,x exclusive or accumulator with memory byte a (a) ? (m) - - * * - imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr,x inc ,x increment byte m (m)+1 a (a)+1 x (x)+1 m (m)+1 m (m)+1 - - * * - dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr,x jmp opr,x jmp ,x unconditional jump pc jump address - - - - - dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr,x jsr opr,x jsr ,x jump to subroutine pc (pc)+n(n=1,2,or 3) push (pcl);sp (sp)-1 push(pch);sp (sp)- 1 pc effective address - - - - - dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda #opr lda opr load accumulator with imm dir a6 b6 ii dd 2 3
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 29 of 33 lda opr lda opr,x lda opr,x lda ,x memory byte a (m) - - * * - ext ix2 ix1 ix c6 d6 e6 f6 hh ll ee ff ff 4 5 4 3 ldx #opr ldx opr ldx opr ldx opr,x ldx opr,x ldx ,x load index register with memory byte x (m) - - * * - imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr,x lsl ,x logical shift left (same as asl) c 0 b7 b0 - - * * * dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr,x lsr ,x logical shift right c 0 b7 b0 - - 0 * * dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x:a ? (x)x(a) 0 - - - 0 inh 42 1 1 neg opr nega negx neg opr,x neg ,x negate byte (twos complement) m -(m) a -(a) x -(x) m -(m) m -(m) - - * * * dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation - - - - - inh 9d 2 ora #opr ora opr ora opr ora opr,x ora opr,x ora ,x logical or accumulator with memory a (a) (m) - - * * - imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff 2 3 4 5 4 3
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 30 of 33 ff rol opr rola rolx rol opr,x rol ,x rotate byte left through carry bit c b7 b0 - - * * * dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr,x ror ,x rotate byte right through carry bit c b7 b0 - - * * * dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff - - - - - inh 9c 2 rti return from interrupt sp (sp)+1; pull(ccr) sp (sp)+1; pull(a) sp (sp)+1; pull(x) sp (sp)+1; pull(pch) sp (sp)+1; pull(pcl) * * * * * inh 80 9 rts return from subroutine sp (sp)+1; pull(pch) sp (sp)+1; pull(pcl) - - - - - inh 81 6 sbc #opr sbc opr sbc opr sbc opr,x sbc opr,x sbc ,x subtract memory byte and carry bit from accumulator a (a)-(m)-(c) - - * * * imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 - - - - 1 inh 99 2 sei set interrupt mask i 1 - 1 - - - inh 9b 2 sta opr sta opr sta opr,x store accumulator in memory m (a) - - * * - dir ext ix2 b7 c7 d7 dd hh ll 4 5 6
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 31 of 33 sta opr,x sta ,x ix1 ix e7 f7 ee ff ff 5 4 stop stop oscillator and enable irq pin - 0 - - - inh 8e 2 stx opr stx opr stx opr,x stx opr,x stx ,x store index register in memory m (x) - - * * - dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 suc #opr sub opr sub opr sub opr,x sub opr,x sub ,x subtract memory byte from accumulator a (a)- (m) - - * * * imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc)+1;push(pc l) sp (sp)-1;push(pc h) sp (sp)-1; push(x) sp (sp)-1; ush(ccr) sp (sp)-1;i 1 pch interrupt vector high byte pcl interrupt vector low byte - 1 - - - inh 83 10 tax transfer accumulator to index register x (a) - - - - - inh 97 2 tst opr tsta tstx tst opr,x test memory byte for negative or zero (m)-$00 - - * * - dir inh inh ix1 3d 4d 5d 6d dd ff 4 3 3 5
?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bm22p14 bm22p14 bm22p14 bm22p14 ?? ?? ?? ?? b l 22p14 user manu al tel 86-21-64850700 web: www.belling.com.cn page 32 of 33 tst ,x ix 7d 4 txa transfer index register to accumulator a (x) - - - - - inh 9f 2 wait stop cpu clock and enable interrupts - 0 - - - inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byt e dd direct address of operand pcl program counter low byt e dd rr direct address of operand and relative offset of branch instruction rel relative addres sing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-b it offset addressing rr relative progra m counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in exte nded addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos compl ement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag ? set or cleared n any bit not affected not affected

▲Up To Search▲

Price & Availability of BL22P14

	To Download BL22P14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .